My U.S. Pat. No. 4,050,030, issued Sept. 20, 1977, to the assignee of the present invention. This patent describes an OFFSET ADJUSTMENT CIRCUIT that can be used to trim the offset of a differential amplifier having JFET input devices. The circuit provides for the use of an external trimming element which produces the trim and the circuit itself provides for cancellation of the offset drift that results from temperature changes.
U.S. Pat. No. 4,496,963, by Robert C. Dobkin and James L. Dunkley is titled SEMICONDUCTOR DEVICE WITH AN ION IMPLANTED STABILIZATION LAYER and issued on Jan. 29, 1985, to the assignee of the present invention. This patent teaches ion implantation and claims the JFET structure that can be incorporated into conventional IC devices.
U.S. Pat. No. 4,079,402, by James E. Solomon and James L. Dunkley, is titled ZENER DIODE INCORPORATING AN ION IMPLANTED LAYER ESTABLISHING THE BREAKDOWN POINT BELOW THE SURFACE, and issued Mar. 14, 1978, to the assignee of the present invention. This patent teaches the use of an ion implanted layer in the fabrication of buried zener diodes adapted for incorporation into IC structures.
The teaching in the above three patents is incorporated herein by reference.
It would be desirable to incorporate a trimming circuit into an operational amplifier IC in which all of the elements are on the chip and in which trimming can be accomplished at either wafer sort or after packaging.